This invention relates to etching of thin films used for semiconductor manufacturing and to improvements in planarization obtained with such films.
Planarization in semiconductor processing involves deposition of a sacrificial layer of material that is then etched back to provide a surface that is smoother than the surface on which the sacrificial layer is deposited. This is illustrated in FIG. 1, in which a substrate 13 has a plurality of metal or other electrical conducting lines 15, 17 and 19 at spaced apart positions. Another layer of metal lines (not shown) is to be deposited above this structure in fabrication of an integrated circuit, and the two sets of lines must be electrically insulated from each other. A layer of an oxide of silicon 21, which will serve as an electrical insulator, is then deposited conformally on the substrate 13 and on the metal lines 15, 17 and 19 so that the metal lines are fully covered with insulating material. Ideally, the oxide of silicon layer 21 would also provide a smooth, planar exposed surface at the top of this structure so that planarization would not be necessary. In practice, the exposed surface of the oxide of silicon layer 21 is "bumpy" wherever a metal line, such as 15, 17 or 19, lies directly underneath. To remedy this and to provide a smoother surface, a sacrificial layer 23 of another insulating material. such as spin-on-glass (SOG), is deposited over the oxide of silicon to provide a smoother exposed surface, and the exposed surface is etched back to a position such as a plane LL indicated in FIG. 1.
Where only the SOG material 23 is exposed, the etch rate can be well controlled because the surface is homogeneous. However, as soon as portions of the underlying oxide of silicon layer 21 are exposed, the homogeneous layer becomes instead a patterned structure with two (or more) distinct materials being etched back. The etch rates of the SOG may be considerably influenced by the amount of the exposed underlying oxide.
Planarization of a patterned structure containing disparate materials, such as the oxide of silicon and SOG layer exposed at the plane in FIG. 1, has been studied by many workers. One goal is improving the quality of such planarized surfaces. Problems arise because of the strong dependence of etch rate of spin-on-glass on certain parameters such as (1) the relative surface area of the oxide of silicon being exposed and etched and (2) the relative percentage the etchant gases such as CHF.sub.3 and C.sub.2 F.sub.6.
Where a patterned structure such as 11 shown in FIG. 1 is developed, containing exposed surfaces of two or more semiconductor processing materials, maintenance of acceptable planarization is difficult at best. The two materials may have very different etch rates for the type of etch chemistry used. During etchback of patterned structures exposed surfaces, such as (1) a stoichiometric silicon dioxide (SD) material and (2) an SOG material, may be plasma etched simultaneously. The spin-on glass may be either a siloxane or a silicate based glass. As seen from FIG. 1, a patterned wafer has SOG covering its surface prior to etchback. In the initial stages of the etch process, the SOG etch rate is fairly constant. However, as the etch proceeds, the underlying oxide is exposed. This exposed oxide tends to increases the etch rate of the SOG adjacent to the exposed oxide. The oxide etch rate remains unchanged during the entire etch process. This concept could be understood by defining a parameter called selectivity given by EQU S(SOG;SD)=r(SOG)/r(SD). (1)
As can be seen from the above discussion, the etch selectivity varies as the SOG etch rate depending on the amount of oxide exposed. In order to maintain good planarization, it is very important to etch the SOG and the oxide at the same rate. In other words, the selectivity during the entire etch process should remain constant and close to unity.
Planarization can be significantly degraded if the SOG etch rate is higher than the etch rate of the oxide (S for a patterned wafer &gt;1). The quality of planarization of a surface developed in a semiconductor processing material is often measured by analyzing the dimensions of a gap in an otherwise-planar surface, as illustrated schematically in FIG. 2. The ratio R of the horizontal width A of the gap to the vertical depth B is a quantitative measure of quality of planarization. The higher the ratio R the better the planarization. For good planarization, the width of a gap relative to its depth should be very large and R&gt;&gt;1. As the value of R decreases, subsequently formed layers may have poor step coverage and may thereby leave behind undesirable stringers after the etch process is terminated.
Many workers in semiconductor processing have sought solutions for this selectivity problem. Vines and Gupta, in "Interlevel Dielectric Planarization With Spin-on Glass Films", VMIC Conf. Proc., 1986, pp. 506-515, discuss the state of the art of interlevel planarization in 1986, noting that a spin-on glass etch rate which is independent of the amount of etchback is desirable for accurate transfer of the smooth topography of a sacrificial layer to an underlying oxide layer.
Hausamann and Mokrisch, in "The Dependence Of Oxide And Spin-on Glass Etchrates On Their Area Ratio", VMIC Confer. Proc., 1988, pp. 293-298, noted the appearance of an unexpected dependence of SOG etch rate on oxide exposure from a plasma enhanced chemical vapor deposition (PECVD) film during etchback for planarization. This observed effect was probably due to oxygen loading. The simultaneous presence of oxide of silicon and SOG on patterned wafers was simulated with unpatterned oxide and SOG wafers and the addition of oxygen as a process gas to the etch chemistry. As can be seen from their results shown in FIG. 3, increasing the amount of oxygen increases the SOG etch rate, whereas the oxide etch rate remains almost unchanged. The authors suggest use of a two-step process. In the first step, approximately 60 percent of the SOG thickness would be removed. In the second step, the oxide and the remaining SOG would be etched with a lower selectivity etchant.
Bogle-Rohwer and Nulty, in "SOG/PSG Etchback Planarization Process", Proc. S.P.I.E., vol. 1392, 1991, pp. 280-290, describe the effect of use of CHF.sub.3, CF.sub.4, C.sub.2 F.sub.6, SF.sub.6 and Ar gases as etchant components for simultaneous etchback of SOG and SD material. Processes having initial selectivity S(SOG;SD)=1.0 were not successful in planarizing structures over patterned wafers. Use of pure CHF.sub.3 or pure Ar as the etchant process gas produced no significant etching of the SOG. Use of fluorine-rich gases, such as CF.sub.4, C.sub.2 F.sub.6 and SF.sub.6, in various mixtures produced adequate etching, although planarization was still a problem.
One persistent problem here is that the SOG etch rate r(SOG) increases with increased exposure of the oxide adjacent to the etch site. Therefore, the SOG etch rate r(SOG) and the selectivity S for any localized region on a wafer may not be constant throughout an etch process. This phenomenon is often referred to as micro-loading. Conventionally, micro-loading has been compensated for by using an SOG material and an etchant that provide a selectivity S(SOG;SD) as low as 0.5 for unpatterned wafers. With a selectivity less than unity on these unpatterned wafers, the SOG etch rate is made deliberately less then the oxide etch rate. This compensates for the increase in SOG etch rate seen on patterned wafers with exposure of the underlying oxide. Thus, a selectivity less than 1 on unpatterned wafers translates to a selectivity close to 1 on patterned wafers. These selectivities are attained by using a fluorine-containing etchant gas, such as CHF.sub.3 combined with a small fraction of CF.sub.4, C.sub.2 F.sub.6 or SF.sub.6, as the process gas. Improvements in control, using this approach, were demonstrated by Bogle-Rohwer and Nulty, op. cit. The effect of the micro-loading problem is reduced somewhat.
Another problem occurs with this approach. Polymer formation within the process gas is enhanced in a fluorine-deficient environment, such as use of a pure CHF.sub.3 etchant, and polymer formation degrades the etch chamber cleanliness and degrades the uniformity of the etch process.
Another persistent problem is that the selectivity S(SOG;SD) for these two materials varies with the fraction f(CHF.sub.3) of CHF.sub.3 present in the etchant gas. This etchant component is a preferred etchant. However, the selectivity S for stoichiometric silicon dioxide SD decreases dramatically with increasing fraction of CHF.sub.3 present.
These problems have prevented achievement of acceptable planarization for a patterned semiconductor structure. What is needed is an approach to planarization of topographies encountered in semiconductor processing that: (1) provides relative insensitivity of SOG etch rates to modest percentage changes in the amount of exposed oxide area and (2) improves planarization and the controllability and reproducibility of the planarization process.